As integrated circuit technologies are scaled, stability in a static memory cell becomes a major concern affecting the design of reliable memory arrays, including, for example, static random access memory (SRAM) arrays. Most static memory cells employ a conventional six-transistor (6-T) architecture. While this memory cell arrangement offers a compact structure, the 6-T memory cell has many disadvantages, particularly its potential inability to scale with overall technology advancements due, at least in part, to stability problems which are often exacerbated as integrated circuit process dimensions shrink. Stability problems generally arise whenever stored voltages on internal nodes of the memory cell are disturbed. As process technologies scale, process-induced variations, as well as fundamental variation sources (e.g., dopant fluctuation effect on threshold voltage, etc.), may result in large threshold voltage variations across a given wafer. This threshold voltage scatter effect essentially magnifies the disturb voltage in 6-T memory cells, which can lead to stability failures in the SRAM array in which the 6-T memory cells are employed.
A recent trend is to employ an eight-transistor (8-T) architecture as illustrated in FIG. 1. The 8-T memory cell 10 is a read assist mechanism that advantageously eliminates disturbs in the memory cell during a read operation. The exemplary 8-T memory cell 10 comprises a static storage element 12 which is selectively connectable to first and second write bit lines (WBL) 14 and 16 via first and second N-channel metal-oxide semiconductor (NMOS) write access transistors 18 and 20, such that a source terminal of transistor 18 is connected to write bit line 14, and a drain terminal of transistor 18 is connected to a first internal node N1 of the storage element 12 and a source terminal of transistor 20 is connected to write bit line 16, and a drain terminal of transistor 20 is connected to a second internal node N2 of the storage element 12. Gate terminals of write access transistors 18 and 20 are connected to a corresponding write word line (WWL) 22 for conveying a write signal. The write access transistors 18 and 20 function to selectively connect the storage element 12 to the write bit lines 14 and 16 in response to the write signal. The static storage element 12 comprises first and second inverters 24 and 26, respectively, configured such that an output of the first inverter 24 is connected to an input of the second inverter 26 at node N2, and an output of the second inverter 26 is connected to an input of the first inverter 24 at node N1.
In order to eliminate read disturbs of the memory cell 10 during the read operation, the memory cell 10 includes a separate read access circuit 28 connected to a corresponding read bit line (RBL) 30 and read word line (RWL) 32 for selectively activating the read access circuit 28. The read access circuit 28 comprises first and second NMOS transistors 34 and 36, respectively, connected in a stacked arrangement. Specifically, a drain terminal of first NMOS transistor 34 is connected to the read bit line 30, a source terminal of the first NMOS transistor 34 is connected to a drain terminal of the second NMOS transistor 36, and a source terminal of the second NMOS transistor 36 is connected to ground. A gate terminal of the first NMOS transistor 34 is connected to the read word line 32 and forms a first input of the read circuit 28, and a gate terminal of the second NMOS transistor 36 is connected to internal node N2 of the storage element 12 and forms a second input of the read access circuit 28.
When reading memory cell 10, an active read signal (e.g., VDD) is applied to the corresponding read word line 32, thereby turning on NMOS transistor 34 in the read access circuit 28. Furthermore, the read bit line 30 is precharged to a high voltage state. When a logical “1” is stored at node N2, NMOS transistor 36 in the read access circuit 28 is turned on, thereby creating an electrical path and allowing current to flow from the read bit line 30 through the read access circuit 28, when the corresponding read bit line 30 is raised above ground potential, between the read bit line 30 and ground through NMOS transistors 34 and 36. However, when a logical “0” is stored at node N2, transistor 36 is turned off and thus the electrical path between read bit line 30 and ground is effectively broken, thereby preventing current from flowing between the read bit line and ground. A sense amplifier, or alternative sensing circuitry, connected to the read bit line 30 is preferably operative to detect a voltage and/or current difference on the read bit line and to equate this difference with the logical state of the memory cell 10.
During the read operation, write access transistors 18 and 20, which are enabled during the write operation, are disabled, such as, for example, by applying a logical “0” to the corresponding write word line 22. Disabling write access transistors 18 and 20 during the read operation serves to electrically isolate the static storage element 12 from the corresponding write bit lines 14 and 16. Furthermore, since the gate terminal of transistor 36, which is connected to node N2 of the storage element 12, has a substantially high impedance, the internal node N2 is essentially electrically isolated from the read bit line 30 during both the read and write operations. The 8-T memory cell 10 provides a mechanism for reading the memory cell which is beneficially decoupled from the mechanism used to write the memory cell. However, as a demand for lower power applications increases, the 8-T memory cell becomes increasingly difficult to write to employing lower voltages.